US 11,705,457 B2
Monolithic multi-FETS
Joseph Carr, Chapel Hill, NC (US); and Ronald S. Cok, Rochester, NY (US)
Assigned to X-Celeprint Limited, Dublin (IE)
Filed by X-Celeprint Limited, Dublin (IE)
Filed on Sep. 17, 2021, as Appl. No. 17/478,311.
Application 17/478,311 is a continuation of application No. 17/096,688, filed on Nov. 12, 2020, granted, now 11,152,395.
Prior Publication US 2022/0149076 A1, May 12, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); H01L 21/78 (2006.01); H01L 21/84 (2006.01); H01L 29/76 (2006.01)
CPC H01L 27/1203 (2013.01) [H01L 21/78 (2013.01); H01L 21/84 (2013.01); H01L 29/76 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A monolithic multi-FET transistor, comprising:
a dielectric layer and an epitaxial layer disposed on the dielectric layer, the epitaxial layer comprising a crystalline semiconductor material and a multi-FET area;
an isolation structure disposed in the epitaxial layer and extending from the dielectric layer through the epitaxial layer to a surface of the epitaxial layer opposite the dielectric layer, the isolation structure surrounding the multi-FET area and dividing the multi-FET area into separate FET portions;
for each separate FET portion of the separate FET portions:
a respective gate dielectric that extends over the separate FET portion that contacts the isolation structure at two separated locations;
a respective gate disposed on the respective gate dielectric;
a respective source disposed on the epitaxial layer on a side of the respective gate;
a respective drain disposed on the epitaxial layer on a side of the respective gate opposite the respective source,
wherein at least the respective gate, the respective source, the respective drain and the separate FET portion of the epitaxial layer form a field-effect transistor (FET);
a gate contact electrically connecting the respective gate of each of the separate FET portions, a source contact electrically connecting the respective source of each of the separate FET portions, and a drain contact electrically connecting the respective drain of each of the FET portions,
wherein at least one of (i) the respective source for two neighboring FET portions of the separate FET portions is a common source disposed over at least a portion of the isolation structure dividing the two neighboring FET portions and (ii) the respective drain for two neighboring FET portions is a common drain disposed over at least a portion of the isolation structure dividing the two neighboring FET portions.