US 11,705,453 B2
Self-aligned gate endcap (SAGE) architecture having local interconnects
Sairam Subramanian, Portland, OR (US); Walid M. Hafez, Portland, OR (US); Sridhar Govindaraju, Portland, OR (US); and Kiran Chikkadi, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 6, 2019, as Appl. No. 16/294,380.
Prior Publication US 2020/0286891 A1, Sep. 10, 2020
Int. Cl. H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 21/308 (2006.01); H01L 23/00 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/3086 (2013.01); H01L 21/3088 (2013.01); H01L 21/76895 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5283 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/785 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first gate structure over a first semiconductor fin;
a second gate structure over a second semiconductor fin;
a gate endcap isolation structure between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures;
a dielectric gate plug over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures; and
a local gate interconnect between the dielectric gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures, wherein the local gate interconnect has a bottommost surface below a bottommost surface of the dielectric gate plug.