US 11,705,449 B2
Through silicon via design for stacking integrated circuits
Kong-Beng Thei, Pao-Shan Village (TW); Dun-Nian Yaung, Taipei (TW); Fu-Jier Fan, Hsinchu (TW); Hsing-Chih Lin, Tainan (TW); Hsiao-Chin Tuan, Taowan (TW); Jen-Cheng Liu, Hsin-Chu (TW); Alexander Kalnitsky, San Francisco, CA (US); and Yi-Sheng Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 9, 2022, as Appl. No. 17/836,076.
Application 17/836,076 is a continuation of application No. 17/370,045, filed on Jul. 8, 2021.
Application 17/370,045 is a continuation of application No. 16/829,176, filed on Mar. 25, 2020, granted, now 11,063,038, issued on Jul. 13, 2021.
Application 16/829,176 is a continuation of application No. 15/989,556, filed on May 25, 2018, granted, now 10,629,592, issued on Apr. 21, 2020.
Prior Publication US 2022/0302108 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 27/06 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01)
CPC H01L 27/0688 (2013.01) [H01L 21/4857 (2013.01); H01L 23/3171 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/562 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/89 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/03916 (2013.01); H01L 2224/80001 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) integrated circuit (IC) comprising:
a first IC die comprising a first semiconductor device disposed in a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate;
a second IC die bonded to the first IC die, wherein the second IC die comprises a second semiconductor device disposed in a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate; and
a plurality of electrical coupling structures arranged at a peripheral region of the first semiconductor device and the second semiconductor device, wherein the plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.