US 11,705,418 B2
Semiconductor package with conductive bump on conductive post including an intermetallic compound layer
Hyunsoo Chung, Hwaseong-si (KR); Taewon Yoo, Seoul (KR); and Myungkee Chung, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 11, 2020, as Appl. No. 17/18,259.
Claims priority of application No. 10-2019-0176181 (KR), filed on Dec. 27, 2019.
Prior Publication US 2021/0202423 A1, Jul. 1, 2021
Int. Cl. H01L 25/065 (2023.01); H01L 25/00 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 23/31 (2006.01)
CPC H01L 24/14 (2013.01) [H01L 23/31 (2013.01); H01L 23/53238 (2013.01); H01L 23/562 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a semiconductor chip including an active surface and a contact pad on the active surface;
a first insulating layer on the active surface, the first insulating layer including a first opening that exposes the contact pad;
a redistribution layer connected to the contact pad, the redistribution layer extending to an upper surface of the first insulating layer;
a second insulating layer on the first insulating layer, the second insulating layer including a second opening that exposes a contact region of the redistribution layer;
a conductive post on the contact region, the conductive post including an intermetallic compound (IMC) layer, the IMC layer being spaced apart from the second insulating layer, an upper surface of the IMC layer being higher than an upper surface of the second insulating layer such that the upper surface of the IMC layer is farther from the active surface of the semiconductor chip compared to the upper surface of the second insulating layer;
an encapsulation layer on the second insulating layer, the encapsulation layer surrounding the conductive post, an upper surface of the encapsulation layer being higher than the upper surface of the IMC layer; and
a conductive bump on an upper surface of the conductive post, the conductive bump contacting the IMC layer, and an interface between the IMC layer and the conductive bump having an uneven surface.