US 11,705,411 B2
Chip package with antenna element
Yung-Ping Chiang, Zhubei (TW); Yi-Che Chiang, Hsinchu (TW); Nien-Fang Wu, Chiayi (TW); Min-Chien Hsiao, Taichung (TW); Chao-Wen Shih, Zhubei (TW); Shou-Zen Chang, Hsinchu (TW); Chung-Shi Liu, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 10, 2021, as Appl. No. 17/315,921.
Application 16/426,365 is a division of application No. 15/625,678, filed on Jun. 16, 2017, granted, now 10,312,203, issued on Jun. 4, 2019.
Application 17/315,921 is a continuation of application No. 16/426,365, filed on May 30, 2019, granted, now 11,004,809.
Claims priority of provisional application 62/433,436, filed on Dec. 13, 2016.
Prior Publication US 2021/0265289 A1, Aug. 26, 2021
Int. Cl. H01L 23/66 (2006.01); H01L 23/00 (2006.01); H01L 23/552 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01); H01L 21/683 (2006.01); H01Q 9/04 (2006.01); H01Q 21/06 (2006.01); H01Q 21/00 (2006.01); H01L 21/56 (2006.01); H01L 23/538 (2006.01); H01Q 1/22 (2006.01); H01Q 21/22 (2006.01)
CPC H01L 23/66 (2013.01) [H01L 21/6835 (2013.01); H01L 23/3121 (2013.01); H01L 23/552 (2013.01); H01L 24/02 (2013.01); H01L 24/13 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/32 (2013.01); H01L 25/0655 (2013.01); H01Q 9/045 (2013.01); H01Q 21/0087 (2013.01); H01Q 21/065 (2013.01); H01L 21/568 (2013.01); H01L 21/6836 (2013.01); H01L 23/3128 (2013.01); H01L 23/5389 (2013.01); H01L 2221/68331 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2223/6644 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/24265 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19104 (2013.01); H01L 2924/3025 (2013.01); H01Q 1/2283 (2013.01); H01Q 21/0075 (2013.01); H01Q 21/22 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package, comprising:
a semiconductor die having a conductive element;
an antenna element over the semiconductor die;
a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element;
a protective layer surrounding the first conductive feature; and
a second conductive feature over the first conductive feature, wherein a portion of the second conductive feature is between the first conductive feature and the protective layer, and the first conductive feature is physically separated from the protective layer by the second conductive feature.