US 11,705,391 B2
Interposer and semiconductor package including the same
Yu-Kyung Park, Hwaseong-si (KR); Seung-kwan Ryu, Seongnam-si (KR); Min-seung Yoon, Yongin-si (KR); and Yun-seok Choi, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 10, 2021, as Appl. No. 17/316,028.
Application 17/316,028 is a division of application No. 16/563,202, filed on Sep. 6, 2019, granted, now 11,081,440.
Claims priority of application No. 10-2019-0034486 (KR), filed on Mar. 26, 2019.
Prior Publication US 2021/0265258 A1, Aug. 26, 2021
Int. Cl. H01L 23/498 (2006.01); H01L 25/18 (2023.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 21/481 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 23/49827 (2013.01); H01L 23/49894 (2013.01); H01L 23/5384 (2013.01); H01L 25/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing an interposer, the method comprising:
preparing a base substrate comprising a through electrode;
forming, on a top surface of the base substrate, an interconnection structure comprising a metal interconnection pattern;
forming, on the interconnection structure, a connection pad electrically connected to the metal interconnection pattern of the interconnection structure;
forming, on the interconnection structure, an upper passivation layer having compressive stress, a bottom region of the upper passivation layer including a first silicon oxide layer, and a bottom surface of the upper passivation layer being coplanar with a bottom surface of the connection pad;
forming, on a bottom surface of the base substrate, a lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; and
forming, on the lower passivation layer, a lower conductive layer electrically connected to the through electrode.