US 11,705,387 B2
Multi-layer interconnection ribbon
Emil Lamco Jocson, Malacca (MY); Mohd Kahar Bajuri, Melaka (MY); and Ryan Tordillo Comadre, Melaka (MY)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Sep. 2, 2020, as Appl. No. 17/10,426.
Prior Publication US 2022/0068770 A1, Mar. 3, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/49527 (2013.01) [H01L 21/4825 (2013.01); H01L 23/3157 (2013.01); H01L 23/49524 (2013.01); H01L 23/49537 (2013.01); H01L 23/49582 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor package assembly, comprising:
a carrier comprising a die attach surface and a contact pad separated from the die attach surface;
a semiconductor die mounted on the die attach surface, the semiconductor die comprising a front side metallization that faces away from the die attach surface;
an interconnect ribbon attached to the semiconductor die and the contact pad such that the interconnect ribbon electrically connects the front side metallization to the contact pad; and
an electrically insulating encapsulant body that encapsulates the semiconductor die and at least part of the interconnect ribbon,
wherein the interconnect ribbon comprises a layer stack of a first metal layer and a second layer formed on top of the first metal layer,
wherein the first metal layer comprises a different metal as the second metal layer,
wherein the first metal layer faces the front side metallization, and
wherein an upper surface of the ribbon is exposed at an upper surface of the encapsulant body.