CPC H01L 23/481 (2013.01) [H01L 21/0337 (2013.01); H01L 21/31111 (2013.01); H01L 21/76897 (2013.01); H01L 29/40117 (2019.08); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02)] | 20 Claims |
1. A memory array comprising:
a vertical stack comprising an uppermost insulating tier, an uppermost conductor tier below the insulating tier, and alternating insulative tiers and wordline tiers below the uppermost conductor tier, the wordline tiers comprising gate regions of individual memory cells, the gate regions individually comprising part of a wordline in individual of the wordline tiers;
channel-material strings extending elevationally through the insulative tiers and the wordline tiers;
the individual memory cells comprising a memory structure laterally between individual of the gate regions and channel material of the channel-material strings;
a wordline-intervening structure extending through the stack between immediately-adjacent of the wordlines; and
a step atop or above an uppermost of the insulative tiers of the alternating insulative tiers and wordline tiers on at least one side of individual of the wordlines, the wordline-intervening structure being atop the step.
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