US 11,705,343 B2
Integrated circuit package and method of forming thereof
Hsien-Wei Chen, Hsinchu (TW); Ming-Fa Chen, Taichung (TW); and Ying-Ju Chen, Tuku Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 24, 2021, as Appl. No. 17/328,001.
Claims priority of provisional application 63/162,629, filed on Mar. 18, 2021.
Prior Publication US 2022/0301890 A1, Sep. 22, 2022
Int. Cl. H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 21/563 (2013.01) [H01L 21/78 (2013.01); H01L 23/31 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
attaching a logic die to a top side of an interposer, the interposer comprising a first die connector and a second die connector on the top side of the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector, the logic die being coupled to the first die connector and to the first dielectric layer, the second die connector being exposed by the logic die;
recessing the first dielectric layer, the recessing exposing at least one sidewall of the second die connector; and
attaching a memory device to the top side of the interposer, the memory device being coupled to the second die connector.