CPC G11C 11/5628 (2013.01) [G11C 16/0483 (2013.01); G11C 16/24 (2013.01); H10B 41/27 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a plurality of memory cells in a plurality of rows;
a plurality of word lines respectively coupled to the plurality of rows of the memory cells; and
a control circuitry coupled to the plurality of memory cells via the plurality of word lines, and configured to:
apply a first program voltage to a first word line of the plurality of word lines, the first word line being coupled to a first row of the plurality of rows of the memory cells;
after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the plurality of word lines, the second word line being coupled to a second row of the plurality of rows of the memory cells; and
after applying the second program voltage to the second word line, perform a pre-charge operation comprising one of:
retaining a first voltage in the first word line, applying a pre-pulse voltage having a first duration to a bit line coupled to, in a column, a memory cell of the plurality of memory cells corresponding to the second word line, and applying a second voltage having a second duration to the second word line, wherein the second voltage is greater than the first voltage, and the first duration is longer than the second duration; or
applying a third voltage to the first word line for lowering a potential of the first word line and retaining a fourth voltage in the second word line, wherein the fourth voltage is greater than the third voltage.
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