CPC G11C 8/18 (2013.01) [G11C 7/106 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); G11C 7/1087 (2013.01); G11C 7/222 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01)] | 20 Claims |
1. A circuit comprising:
a plurality of registers, each register comprising static random access memory (SRAM) cells;
a read port configured to receive a read address;
a write port configured to receive a write address;
a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers; and
a control circuit configured to, responsive to a clock signal and read and write enable signals, cause the selection circuit, the latch circuit, and the decoder to:
select a first register of the plurality of registers in a read operation based on the read address, and
select a second register of the plurality of registers in a write operation based on the write address.
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