US 11,705,174 B2
Integrated circuit with asymmetric arrangements of memory arrays
Xiu-Li Yang, Shanghai (CN); He-Zhou Wan, Shanghai (CN); Kuan Cheng, Shanghai (CN); and Ching-Wei Wu, Nantou County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); and TSMC CHINA COMPANY LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); and TSMC CHINA COMPANY LIMITED, Shanghai (CN)
Filed on Mar. 25, 2022, as Appl. No. 17/704,644.
Application 17/704,644 is a continuation of application No. 16/794,104, filed on Feb. 18, 2020, granted, now 11,289,141.
Claims priority of application No. 201911411056.5 (CN), filed on Dec. 31, 2019.
Prior Publication US 2022/0215868 A1, Jul. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/10 (2006.01); G11C 8/12 (2006.01); G11C 8/14 (2006.01)
CPC G11C 8/10 (2013.01) [G11C 8/12 (2013.01); G11C 8/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a plurality of memory cells comprising a first array of memory cells and a second array of memory cells;
a first pair of complementary data lines coupled to the first array of memory cells; and
a second pair of complementary data lines, different from the first pair of complementary data lines, coupled to the second array of memory cells;
wherein a number of memory cells in the first array of memory cells is different from a number of memory cells in the second array of memory cells.