CPC G11C 8/10 (2013.01) [G11C 8/12 (2013.01); G11C 8/14 (2013.01)] | 20 Claims |
1. An integrated circuit, comprising:
a plurality of memory cells comprising a first array of memory cells and a second array of memory cells;
a first pair of complementary data lines coupled to the first array of memory cells; and
a second pair of complementary data lines, different from the first pair of complementary data lines, coupled to the second array of memory cells;
wherein a number of memory cells in the first array of memory cells is different from a number of memory cells in the second array of memory cells.
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