CPC G11C 7/222 (2013.01) [G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 8/18 (2013.01); G11C 29/023 (2013.01)] | 20 Claims |
1. A memory device comprising:
a first register configured to store a first code value;
a second register configured to store a second code value;
a third register storing first training information;
a duty cycle adjuster configured to select one of the first code value and the second code value according to operation mode information and to adjust a duty of a data transmission clock according to the selected code value; and
a duty cycle monitor configured to perform first training on a write path according to a training request from an external device and to perform second training on a read path,
wherein the first code value is transmitted from the external device,
the second code value corresponds to a result value of the second training, and the first training information includes a result value of the first training.
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