US 11,705,169 B2
Trim/test interface for devices with low pin count or analog or no-connect pins
Rajat Chauhan, Karnataka (IN); Divya Kaur, Delhi (IN); and Rishav Gupta, Punjab (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Nov. 30, 2021, as Appl. No. 17/537,872.
Claims priority of application No. 202041056137 (IN), filed on Dec. 23, 2020.
Prior Publication US 2022/0238143 A1, Jul. 28, 2022
Int. Cl. G11C 7/10 (2006.01); H03K 19/007 (2006.01)
CPC G11C 7/1084 (2013.01) [H03K 19/007 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A packaged integrated circuit (IC) device comprising:
packaging enclosing an IC die, the packaging comprising conductive pins including a first pin configured to receive analog input signals in a normal mode of the IC device and to receive a digital test mode entry clock signal as a key to entry of the IC device into a test mode in which the IC device is configured to receive test or trim inputs on one or more of the pins and to provide test outputs on the one or more of the pins or to calibrate the IC device by programming trim bit registers in a nonvolatile memory in the IC device, the IC die comprising a power-on reset (POR) generator and a test interface architecture, the test interface architecture comprising:
digital logic configured to transition the IC device from the normal mode to the test mode; and
a floating-pin-tolerant always-on complementary metal-oxide-semiconductor (CMOS) input buffer coupled at a first end to the first pin and at a second end to an input of the digital logic.