US 11,705,167 B2
Memory circuit, method and device for controlling pre-charging of memory
Liang Zhang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 9, 2021, as Appl. No. 17/470,895.
Application 17/470,895 is a continuation of application No. PCT/CN2021/106734, filed on Jul. 16, 2021.
Claims priority of application No. 202110352501.6 (CN), filed on Mar. 31, 2021.
Prior Publication US 2022/0319560 A1, Oct. 6, 2022
Int. Cl. G11C 7/10 (2006.01); G11C 5/06 (2006.01); G11C 7/22 (2006.01); G11C 5/14 (2006.01)
CPC G11C 7/1048 (2013.01) [G11C 5/06 (2013.01); G11C 5/14 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); G11C 7/222 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory circuit, comprising:
a pre-charging circuit, comprising a first pre-charging unit, a second pre-charging unit, a first power supply terminal, a second power supply terminal, a first control terminal, a second control terminal and a data terminal, wherein the first pre-charging unit is connected with the first power supply terminal, the first control terminal and the data terminal; the second pre-charging unit is connected with the second power supply terminal, the second control terminal and the data terminal; and a first pre-charging voltage is input into the first power supply terminal, and a second pre-charging voltage is input into the second power supply terminal; and
a control circuit, wherein a first output terminal of the control circuit is connected with the first control terminal, and a second output terminal of the control circuit is connected with the second control terminal;
wherein the control circuit is configured to:
in response to a memory being not in a row active state, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be connected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected;
in response to the memory being in the row active state and not performing a reading-writing operation, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected;
in response to the memory being in the row active state, during a preset time period after the reading-writing operation is started, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be connected; and
in response to the memory being in the row active state, after the preset time period after the reading-writing operation is started, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected.