CPC G11C 7/1048 (2013.01) [G11C 5/06 (2013.01); G11C 5/14 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); G11C 7/222 (2013.01)] | 16 Claims |
1. A memory circuit, comprising:
a pre-charging circuit, comprising a first pre-charging unit, a second pre-charging unit, a first power supply terminal, a second power supply terminal, a first control terminal, a second control terminal and a data terminal, wherein the first pre-charging unit is connected with the first power supply terminal, the first control terminal and the data terminal; the second pre-charging unit is connected with the second power supply terminal, the second control terminal and the data terminal; and a first pre-charging voltage is input into the first power supply terminal, and a second pre-charging voltage is input into the second power supply terminal; and
a control circuit, wherein a first output terminal of the control circuit is connected with the first control terminal, and a second output terminal of the control circuit is connected with the second control terminal;
wherein the control circuit is configured to:
in response to a memory being not in a row active state, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be connected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected;
in response to the memory being in the row active state and not performing a reading-writing operation, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected;
in response to the memory being in the row active state, during a preset time period after the reading-writing operation is started, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be connected; and
in response to the memory being in the row active state, after the preset time period after the reading-writing operation is started, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected.
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