US 11,705,166 B2
Memory device including on-die-termination circuit
Eun-Ji Kim, Suwon-si (KR); Jung-June Park, Seoul (KR); Jeong-Don Ihm, Seongnam-si (KR); Byung-Hoon Jeong, Hwaseong-si (KR); and Young-Don Choi, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 23, 2021, as Appl. No. 17/182,357.
Application 17/182,357 is a continuation of application No. 16/875,163, filed on May 15, 2020, granted, now 10,964,360.
Application 16/875,163 is a continuation of application No. 16/058,709, filed on Aug. 8, 2018, granted, now 10,672,436, issued on Jun. 2, 2020.
Claims priority of application No. 10-2017-0146179 (KR), filed on Nov. 3, 2017.
Prior Publication US 2021/0201964 A1, Jul. 1, 2021
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1048 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 2207/105 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An operating method of a storage device including a NAND flash memory device and a controller configured to control the NAND flash memory device, the method comprising:
transmitting a command and an address, via an input/output line, from the controller to the NAND flash memory device;
transmitting an on-die Termination (ODT) signal, via a single ODT signal line, from the controller to the NAND flash memory device including a first memory chip including a first ODT circuit, a second memory chip including a second ODT circuit, a third memory chip including a third ODT circuit, and a fourth memory chip including a fourth ODT circuit, the ODT signal defining an enable period for at least one of the first to fourth ODT circuits;
transmitting a first chip enable signal, via a first chip enable signal line, from the controller to the first and second memory chips;
transmitting a second chip enable signal, via a second chip enable signal line, from the controller to the third and fourth memory chips; and
providing a first ODT resistor or a second ODT resistor by the at least one of the first to fourth ODT circuits, in response to the ODT signal, at least one of the first and second chip enable signals, and the address.