US 11,705,165 B2
Method and system for adjusting memory, and semiconductor device
Shu-Liang Ning, Hefei (CN); Jun He, Hefei (CN); Zhan Ying, Hefei (CN); and Jie Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Oct. 26, 2021, as Appl. No. 17/510,453.
Application 17/510,453 is a continuation of application No. PCT/CN2021/106060, filed on Jul. 13, 2021.
Claims priority of application No. 202010880935.9 (CN), filed on Aug. 27, 2020.
Prior Publication US 2022/0068321 A1, Mar. 3, 2022
Int. Cl. G11C 7/06 (2006.01); G11C 7/12 (2006.01); G11C 7/04 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01)
CPC G11C 7/06 (2013.01) [G11C 7/04 (2013.01); G11C 7/1093 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for adjusting a memory, wherein the memory comprises a transistor, a gate of the transistor is electrically connected with a Word Line (WL) of the memory, one of a source and a drain of the transistor is electrically connected with a Bit Line (BL) of the memory through a sense amplifier, and another one of the source and the drain of the transistor is electrically connected with a storage capacitor of the memory, the method comprising:
acquiring a mapping relationship between a temperature of the transistor, an equivalent width-length ratio of a sense amplifier transistor in the sense amplifier, and an actual time at which data is written into the memory;
acquiring a current temperature of the transistor; and
adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.