US 11,704,766 B2
Method and device for latency reduction of an image processing pipeline
Bertrand Nepveu, Montreal (CA); Marc-Andre Chenier, Saint-Hyacinthe (CA); Yan Cote, Notre-Dame-de-L'ile-Perrot (CA); and Yves Millette, Santa Clara, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 2, 2022, as Appl. No. 17/979,630.
Application 17/979,630 is a continuation of application No. 17/215,151, filed on Mar. 29, 2021, granted, now 11,521,291.
Claims priority of provisional application 63/007,005, filed on Apr. 8, 2020.
Prior Publication US 2023/0053205 A1, Feb. 16, 2023
Int. Cl. G06T 1/20 (2006.01); G06T 19/00 (2011.01); G06T 7/73 (2017.01); G06T 15/20 (2011.01); G06T 5/00 (2006.01); G06T 15/00 (2011.01)
CPC G06T 1/20 (2013.01) [G06T 5/003 (2013.01); G06T 5/007 (2013.01); G06T 7/73 (2017.01); G06T 15/005 (2013.01); G06T 15/20 (2013.01); G06T 19/006 (2013.01)] 21 Claims
OG exemplary drawing
 
21. The non-transitory memory of claim 16, wherein the one or more programs further cause the device to:
present the graphical environment via a display device.