US 11,704,467 B2
Automated balanced global clock tree synthesis in multi level physical hierarchy
Ashima Sahil Dabare, Noida (IN); Sanjiv Mathur, Noida (IN); Anusha Reddy Sindhwala, Bangalore (IN); Prakasha Karkada Holla, Bangalore (IN); Sivakumar Arulanantham, Hillsboro, OR (US); Srinivasan Krishnamurthy, Hillsboro, OR (US); Chun-Cheng Chi, Mountain View, CA (US); and Shih-Pin Hung, Hsinchu (TW)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jun. 16, 2021, as Appl. No. 17/349,400.
Claims priority of application No. 202041025226 (IN), filed on Jun. 16, 2020.
Prior Publication US 2021/0390242 A1, Dec. 16, 2021
Int. Cl. G06F 30/396 (2020.01); G06F 30/398 (2020.01); G06F 30/394 (2020.01)
CPC G06F 30/396 (2020.01) [G06F 30/394 (2020.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for building a global clock tree, comprising:
inserting a plurality of clock drivers at symmetric locations in one or more hierarchy levels of a plurality of hierarchy levels of an integrated circuit (IC) design;
generating one or more routes between the plurality of clock drivers by routing one or more nets to one or more of within across the one or more hierarchy levels of the plurality of hierarchy levels;
matching symmetric routes of the one or more routes at each of the one or more hierarchy levels; and
placing one or more ports at one or more signal entry points where routes of the one or more routes across physical hierarchy blocks.