CPC G06F 30/396 (2020.01) [G06F 30/394 (2020.01); G06F 30/398 (2020.01)] | 20 Claims |
1. A method for building a global clock tree, comprising:
inserting a plurality of clock drivers at symmetric locations in one or more hierarchy levels of a plurality of hierarchy levels of an integrated circuit (IC) design;
generating one or more routes between the plurality of clock drivers by routing one or more nets to one or more of within across the one or more hierarchy levels of the plurality of hierarchy levels;
matching symmetric routes of the one or more routes at each of the one or more hierarchy levels; and
placing one or more ports at one or more signal entry points where routes of the one or more routes across physical hierarchy blocks.
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