CPC G06F 12/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G06F 2212/657 (2013.01); G11C 2216/14 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a memory device; and
an accelerator configured to generate a set of entries for mapping logical block addresses to physical addresses of the memory device, the set of entries comprising:
a first entry for mapping a first logical block address to a first physical address and a second physical address; and
a second entry for mapping a second logical block address to the second physical address and a third physical address.
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