US 11,704,252 B2
Dual address encoding for logical-to-physical mapping
Giuseppe Cariello, Boise, ID (US); and Jonathan S. Parry, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 6, 2021, as Appl. No. 17/495,410.
Application 17/495,410 is a continuation of application No. 16/869,397, filed on May 7, 2020, granted, now 11,144,471.
Prior Publication US 2022/0100674 A1, Mar. 31, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/00 (2006.01); G06F 12/10 (2016.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01)
CPC G06F 12/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G06F 2212/657 (2013.01); G11C 2216/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device; and
an accelerator configured to generate a set of entries for mapping logical block addresses to physical addresses of the memory device, the set of entries comprising:
a first entry for mapping a first logical block address to a first physical address and a second physical address; and
a second entry for mapping a second logical block address to the second physical address and a third physical address.