US 11,704,158 B2
Managing processing system efficiency
Liqun Cheng, Foster City, CA (US); Rama Krishna Govindaraju, San Jose, CA (US); Haishan Zhu, Austin, TX (US); David Lo, Palo Alto, CA (US); Parthasarathy Ranganathan, San Jose, CA (US); and Nishant Patil, Sunnyvale, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Jan. 29, 2021, as Appl. No. 17/162,682.
Application 17/162,682 is a continuation of application No. 16/198,583, filed on Nov. 21, 2018, granted, now 10,908,964.
Claims priority of provisional application 62/589,535, filed on Nov. 21, 2017.
Prior Publication US 2021/0224129 A1, Jul. 22, 2021
Int. Cl. G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06N 20/00 (2019.01)
CPC G06F 9/5038 (2013.01) [G06F 9/4881 (2013.01); G06F 9/505 (2013.01); G06F 9/5016 (2013.01); G06F 9/5061 (2013.01); G06F 9/5083 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A method implemented using a system comprising a hardware accelerator coupled to a plurality of processors, the method comprising:
identifying a splitting of the plurality of processors among:
a first domain that performs tasks that support the hardware accelerator in accelerating execution of a machine-learning (ML) workload; and
a second, different domain;
during runtime of the system, obtaining memory usage measurements that characterize usage of system memory by the first domain and the second domain; and
adjusting, based on the memory usage measurements, a configuration of (i) the first domain, (ii) the second domain, or (iii) both; and
adjusting utilization of the system memory by the plurality of processors in response to adjusting the configuration.