US 11,704,131 B2
Moving entries between multiple levels of a branch predictor based on a performance loss resulting from fewer than a pre-set number of instructions being stored in an instruction cache register
Chen Chen, Shanghai (CN); Tao Jiang, Hangzhou (CN); and Dongqi Liu, Hangzhou (CN)
Assigned to Alibaba Group Holding Limited, Grand Cayman (KY)
Filed by ALIBABA GROUP HOLDING LIMITED, Grand Cayman (KY)
Filed on Aug. 14, 2020, as Appl. No. 16/994,052.
Claims priority of application No. 201910901489.2 (CN), filed on Sep. 23, 2019.
Prior Publication US 2021/0089315 A1, Mar. 25, 2021
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 11/34 (2006.01)
CPC G06F 9/3806 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30058 (2013.01); G06F 9/30098 (2013.01); G06F 9/3814 (2013.01); G06F 9/3844 (2013.01); G06F 11/3466 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An instruction processing device, comprising:
a first-level branch target buffer, configured to store entries of a first plurality of branch instructions;
a second-level branch target buffer, configured to store entries of a second plurality of branch instructions, wherein the entries in the first-level branch target buffer are accessed faster than the entries in the second-level branch target buffer;
an instruction fetch unit coupled to the first-level branch target buffer and the second-level branch target buffer, the instruction fetch unit including circuitry configured to:
simultaneously search the first-level branch target buffer and the second-level branch target buffer for one or more entries corresponding to the first branch instruction;
if the one or more entries corresponding to the first branch instruction are found in the first-level branch target buffer, fetch a next instruction based on a target address in the one or more entries;
if the one or more entries corresponding to the first branch instruction are not found in the first-level branch target buffer,
determine whether there is a performance loss according to whether at least a pre-set number of instructions are stored in an instruction cache register; and
if it is determined that there is the performance loss, add the one or more entries corresponding to the first branch instruction into the first-level branch target buffer; and
an execution unit including circuitry configured to execute the first branch instruction.