CPC G06F 9/3806 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30058 (2013.01); G06F 9/30098 (2013.01); G06F 9/3814 (2013.01); G06F 9/3844 (2013.01); G06F 11/3466 (2013.01)] | 14 Claims |
1. An instruction processing device, comprising:
a first-level branch target buffer, configured to store entries of a first plurality of branch instructions;
a second-level branch target buffer, configured to store entries of a second plurality of branch instructions, wherein the entries in the first-level branch target buffer are accessed faster than the entries in the second-level branch target buffer;
an instruction fetch unit coupled to the first-level branch target buffer and the second-level branch target buffer, the instruction fetch unit including circuitry configured to:
simultaneously search the first-level branch target buffer and the second-level branch target buffer for one or more entries corresponding to the first branch instruction;
if the one or more entries corresponding to the first branch instruction are found in the first-level branch target buffer, fetch a next instruction based on a target address in the one or more entries;
if the one or more entries corresponding to the first branch instruction are not found in the first-level branch target buffer,
determine whether there is a performance loss according to whether at least a pre-set number of instructions are stored in an instruction cache register; and
if it is determined that there is the performance loss, add the one or more entries corresponding to the first branch instruction into the first-level branch target buffer; and
an execution unit including circuitry configured to execute the first branch instruction.
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