CPC G06F 9/3001 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30145 (2013.01); G06F 9/3802 (2013.01)] | 23 Claims |
1. A processor comprising:
fetch circuitry to fetch a vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier;
decode circuitry to decode the fetched vector multiplication instruction; and
execution circuitry to, on each of a plurality of pairs of corresponding fixed-sized multiple-bit signed elements of the identified first and second sources, execute the decoded vector multiplication instruction to:
generate a double-sized product of each pair of fixed-sized multiple-bit signed elements, the double-sized product being represented by at least twice a number of bits of the fixed-size,
generate, for each double-sized product, a result of the fixed-size by rounding the double-sized product, and
store each fixed-sized result into a corresponding fixed-sized element of the identified destination.
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