US 11,704,124 B2
Instructions for vector multiplication of unsigned words with rounding
Venkateswara R. Madduri, Austin, TX (US); Carl Murray, Dublin (IE); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Mark J. Charney, Lexington, MA (US); Robert Valentine, Kiryat Tivon (IL); and Jesus Corbal, King City, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 11, 2022, as Appl. No. 17/573,556.
Application 17/573,556 is a continuation of application No. 16/642,778, granted, now 11,221,849, issued on Jan. 11, 2022, previously published as PCT/US2017/053649, filed on Sep. 27, 2017.
Prior Publication US 2022/0318009 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/22 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3001 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30145 (2013.01); G06F 9/3802 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A processor comprising:
fetch circuitry to fetch a vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier;
decode circuitry to decode the fetched vector multiplication instruction; and
execution circuitry to, on each of a plurality of pairs of corresponding fixed-sized multiple-bit signed elements of the identified first and second sources, execute the decoded vector multiplication instruction to:
generate a double-sized product of each pair of fixed-sized multiple-bit signed elements, the double-sized product being represented by at least twice a number of bits of the fixed-size,
generate, for each double-sized product, a result of the fixed-size by rounding the double-sized product, and
store each fixed-sized result into a corresponding fixed-sized element of the identified destination.