CPC G06F 3/0634 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0611 (2013.01); G06F 3/0625 (2013.01); G06F 3/0638 (2013.01); G06F 3/0673 (2013.01); G06F 3/0683 (2013.01); G06F 12/02 (2013.01); G06F 12/0607 (2013.01); G06F 15/781 (2013.01); G06F 12/0646 (2013.01); G06F 13/4282 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01); Y02D 10/00 (2018.01)] | 20 Claims |
1. A system comprising:
a first processor in an improved performance mode connected to each of a first port and a second port via a connection circuit;
a second processor in a reduced power consumption mode connected to only one of the first port and the second port via the connection circuit; and
an address remapping circuit in communication with the first processor and configured to remap an original address to a remapped address when a memory accessed by the first processor is shared with the second processor.
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