US 11,704,031 B2
Memory system and SOC including linear address remapping logic
Dongsik Cho, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 22, 2021, as Appl. No. 17/155,503.
Application 17/155,503 is a continuation of application No. 16/983,389, filed on Aug. 3, 2020.
Application 16/983,389 is a continuation of application No. 16/940,687, filed on Jul. 28, 2020, granted, now 11,573,716.
Application 16/940,687 is a continuation of application No. 16/215,827, filed on Dec. 11, 2018, granted, now 11,169,722.
Application 16/215,827 is a continuation of application No. 15/424,019, filed on Feb. 3, 2017, granted, now 10,817,199, issued on Oct. 27, 2020.
Application 15/424,019 is a continuation of application No. 14/990,975, filed on Jan. 8, 2016, abandoned.
Application 14/990,975 is a continuation of application No. 13/803,269, filed on Mar. 14, 2013, granted, now 9,256,531, issued on Feb. 9, 2016.
Claims priority of application No. 10-2012-0065624 (KR), filed on Jun. 19, 2012.
Prior Publication US 2021/0141549 A1, May 13, 2021
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 15/78 (2006.01); G06F 13/42 (2006.01)
CPC G06F 3/0634 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0611 (2013.01); G06F 3/0625 (2013.01); G06F 3/0638 (2013.01); G06F 3/0673 (2013.01); G06F 3/0683 (2013.01); G06F 12/02 (2013.01); G06F 12/0607 (2013.01); G06F 15/781 (2013.01); G06F 12/0646 (2013.01); G06F 13/4282 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a first processor in an improved performance mode connected to each of a first port and a second port via a connection circuit;
a second processor in a reduced power consumption mode connected to only one of the first port and the second port via the connection circuit; and
an address remapping circuit in communication with the first processor and configured to remap an original address to a remapped address when a memory accessed by the first processor is shared with the second processor.