US 11,703,527 B2
Voltage detection circuit and charge pump circuit
Rumin Ji, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 9, 2021, as Appl. No. 17/469,980.
Application 17/469,980 is a continuation of application No. PCT/CN2021/103598, filed on Jun. 30, 2021.
Claims priority of application No. 202010921793.6 (CN), filed on Sep. 4, 2020.
Prior Publication US 2022/0074978 A1, Mar. 10, 2022
Int. Cl. G01R 19/32 (2006.01); H02M 3/07 (2006.01); G11C 11/4074 (2006.01)
CPC G01R 19/32 (2013.01) [H02M 3/07 (2013.01); G11C 11/4074 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A voltage detection circuit, comprising:
a voltage raising circuit configured to adjust a voltage to be measured and output an adjusted voltage, wherein the adjusted voltage is equal to a sum of the voltage to be measured and a reference voltage; and
a current generation circuit connected to the voltage raising circuit and configured to provide a constant current to the voltage raising circuit,
wherein the reference voltage is generated by a combination of a first voltage with a positive temperature coefficient and a second voltage with a negative temperature coefficient, and
wherein the current generation circuit comprises:
a first switch transistor having a first terminal connected to a power supply voltage, a second terminal connected with a first node, and a control terminal connected with a second node;
a second switch transistor having a first terminal connected to the power supply voltage, a second terminal connected with a third node, and a control terminal connected with the second node;
a third switch transistor having a first terminal connected to the power supply voltage, a control terminal connected with the second node, and a second terminal configured to output the constant current;
a first bipolar transistor having an emitter connected with the first node through a first resistor, and a collector and a base that are grounded;
a second bipolar transistor having an emitter connected with the third node, and a collector and a base that are grounded; and
an amplifier having a non-inverting input terminal connected with the first node, an inverting input terminal connected with the third node, and an output terminal connected with the second node.