| US 7,565,588 B2 | ||
| Semiconductor device and data storage apparatus | ||
| Katsuya Nakashima, Nagasaki (Japan); Kazuhiro Suzuki, Kanagawa (Japan); Satoshi Yamakawa, Tokyo (Japan); Toshiyuki Nishihara, Kanagawa (Japan); and Yukihisa Tsuneda, Kanagawa (Japan) | ||
| Assigned to Sony Corporation, (Japan) | ||
| Filed on Dec. 01, 2006, as Appl. No. 11/607,029. | ||
| Claims priority of application No. P2005-354063 (JP), filed on Dec. 07, 2005; and application No. P2006-138120 (JP), filed on May 17, 2006. | ||
| Prior Publication US 2007/0130488 A1, Jun. 07, 2007 | ||
| Int. Cl. G11C 29/00 (2006.01); G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—718 [714/726] | 27 Claims |
| 1. A semiconductor device comprising:
a cell array having cells for data storage arranged in an array;
a plurality of buffers configured to latch read data from the cell array in units of pages;
an output circuit configured to output read data; and
a data transfer circuit configured to sequentially transfer read data in units of pages latched in the buffer to the output
circuit,
wherein the data transfer circuit includes:
at least one scan register train, each of the at least one scan register train including plurality of serially connected scan
registers, each of the scan registers being operated at every clock cycle;
each scan register in a given scan register train including a register and a multiplexer, in each scan register, an output
of the multiplexer is connected to an input of the register, and an input of the multiplexer is connected to an output of
a previous scan register in the given scan register train.
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