US 7,565,580 B2
Method and system for testing network device logic
Bradley S. Sonksen, Rancho Santa Margarita, Calif. (US); Aklank H. Shah, Ladera Ranch, Calif. (US); and James M. Hamada, Jr., Irvine, Calif. (US)
Assigned to QLOGIC, Corporation, Aliso Viejo, Calif. (US)
Filed on Aug. 10, 2005, as Appl. No. 11/201,036.
Prior Publication US 2007/0036082 A1, Feb. 15, 2007
Int. Cl. G06F 11/00 (2006.01)
U.S. Cl. 714—44  [714/56] 23 Claims
OG exemplary drawing
 
1. A test module for testing PCI Express device logic, wherein the test module is placed between a PCI Express Port Logic and PCI Express Transaction Handler (“PTH”) comprising:
a packet counter that counts test packets that are received from a buffer in the PCI Express port logic and written in a memory of the test module; and an idle timer that counts time that has expired after a last test packet has been received by the memory module of the test module; wherein if the packet counter value exceeds a threshold value then all test packets residing in the memory of the test module are sent to the PTH for testing and if the idle timer expires at any given instance, then all the test packets in the memory of the test module are sent to the PTH.