| US 7,565,121 B2 | ||
| Clock noise canceling circuit | ||
| Joo Yul Ko, Kyungki-do (Korea, Republic of); Hak Sun Kim, Daejeon (Korea, Republic of); Won Tae Choi, Kyungki-do (Korea, Republic of); and Won Wook So, Kyungki-do (Korea, Republic of) | ||
| Assigned to Samsung Electro-Mechanics Co., Ltd., Suwon, Kyungki-Do (Korea, Republic of) | ||
| Filed on Dec. 04, 2006, as Appl. No. 11/566,587. | ||
| Claims priority of application No. 10-2006-0015435 (KR), filed on Feb. 17, 2006. | ||
| Prior Publication US 2007/0195915 A1, Aug. 23, 2007 | ||
| Int. Cl. H04B 7/08 (2006.01) | ||
| U.S. Cl. 455—136 [455/138; 455/232.1; 455/296] | 6 Claims |
| 1. A clock noise canceling circuit comprising:
a coupler for extracting a signal from a clock signal;
a filter for selecting a harmonic component of a preset frequency in the extraction signal from the coupler;
a phase shifter for phase inverting the harmonic component of the preset frequency from the filter;
an automatic gain control amplifier for amplifying the phase-inverted harmonic component from the phase shifter;
a combiner for combining the amplified component from the phase shifter with the clock signal to eliminate the harmonic component
of the preset frequency from the clock signal;
a power detector for detecting a power level of the harmonic component of the preset frequency in an output signal of the
combiner; and
a controller for controlling gain of the automatic gain control amplifier based on the power level of the harmonic component
detected by the power detector, thereby canceling noises.
|