| US 7,564,728 B2 | ||
| Semiconductor memory device and its driving method | ||
| Hi-Hyun Han, Ichon-shi (Korea, Republic of) | ||
| Assigned to Hynix Semiconductor, Inc., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jun. 30, 2006, as Appl. No. 11/477,392. | ||
| Claims priority of application No. 10-2005-0091675 (KR), filed on Sep. 29, 2005; and application No. 10-2005-0134012 (KR), filed on Dec. 29, 2005. | ||
| Prior Publication US 2007/0070746 A1, Mar. 29, 2007 | ||
| Int. Cl. G11C 7/12 (2006.01) | ||
| U.S. Cl. 365—203 [365/226; 365/227; 365/189.09] | 16 Claims |
| 5. A semiconductor memory device having a bit line sense amplifier shared by an upper cell block and a lower cell block, comprising:
an equalization signal generating unit for generating an equalization signal in response to an upper cell block selection
signal and a lower cell block selection signal; and
a voltage provider for providing the equalization signal generating unit with an operational voltage,
wherein the voltage provider provides the equalization signal generating unit with a first voltage for an initial period and
then provides a second voltage having a lower level than the first voltage after a predetermined time period and includes:
a repeating unit for repeating the equalization signal; and
a pull-up controlling unit for providing the repeating unit with the first and second voltages in response to the equalization
signal.
|