| US 7,564,717 B2 | ||
| Semiconductor memory device | ||
| Kazuhiko Sato, Yokohama (Japan); Hidetoshi Saito, Yamato (Japan); and Kiyotaka Uchigane, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 24, 2007, as Appl. No. 11/923,200. | ||
| Claims priority of application No. 2006-294932 (JP), filed on Oct. 30, 2006. | ||
| Prior Publication US 2008/0291740 A1, Nov. 27, 2008 | ||
| Int. Cl. G11C 11/34 (2006.01) | ||
| U.S. Cl. 365—185.23 [365/226] | 20 Claims |
| 1. A semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells each having a charge storage layer and a control gate formed on an
inter-gate insulating film on the charge storage layer are arranged in a matrix;
word lines each of which connects the control gates of the memory cells on the same row together in the memory cell array;
a row decoder which selects a word line, and applies a voltage to the selected word line; and
a voltage generator which generates a boosted voltage, and outputs the boosted voltage as the voltage,
the voltage generator including:
a comparator which compares a first voltage with a second voltage, and outputs a comparison result signal;
a constant current circuit which generates a first control signal in accordance with the comparison result signal output from
the comparator;
a first delay circuit which generates a second control signal by delaying the comparison result signal output from the comparator;
and
a charge pump circuit which generates the boosted voltage in response to the first control signal and the second control signal.
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