| US 7,564,116 B2 | ||
| Printed circuit board with embedded capacitors therein and manufacturing process thereof | ||
| Jin Yong Ahn, Daejeon (Korea, Republic of); Cheol Seong Hwang, Seoul (Korea, Republic of); Sung Kun Kim, Seoul (Korea, Republic of); Chang Sup Ryu, Daejeon (Korea, Republic of); Suk-Hyeon Cho, Daejeon (Korea, Republic of); and Ho Sik Jeon, Chungcheongbuk-do (Korea, Republic of) | ||
| Assigned to Samsung Electro-Mechanics Co., Ltd., Gyeonggi-Do (Korea, Republic of) | ||
| Filed on Jan. 18, 2008, as Appl. No. 12/16,919. | ||
| Application 12/016919 is a division of application No. 11/365219, filed on Feb. 28, 2006, granted, now 7,378,326. | ||
| Claims priority of application No. 10-2005-0017333 (KR), filed on Feb. 28, 2006. | ||
| Prior Publication US 2008/0110667 A1, May 15, 2008 | ||
| Int. Cl. H01L 29/00 (2006.01); H05K 3/30 (2006.01); H01L 21/20 (2006.01) | ||
| U.S. Cl. 257—532 [257/535; 257/E21.008; 257/E21.35; 29/832; 29/25.41; 29/25.42; 438/393; 438/957] | 10 Claims |
| 1. A printed circuit board having embedded capacitors therein, comprising:
a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers
including bottom electrodes and circuit patterns;
alumina dielectric layers formed on the first circuit layers through atomic layer deposition;
second circuit layers formed on the dielectric layers, the second circuit layers including top electrodes and circuit patterns;
one-sided copper-clad laminates formed on the second circuit layers;
blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and
plating layers formed in the blind via-holes and the through-holes,
wherein the second circuit layers include metal oxide seed layers of indium tin oxide (ITO) or ruthenium oxide (RuO2) on the dielectric layers, and copper plating layers on the metal oxide seed layers.
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