| US 7,564,107 B2 | ||
| Power semiconductor device including a terminal structure | ||
| Satoshi Yanagisawa, Kawasaki (Japan); Satoshi Aida, Kawasaki (Japan); Shigeo Kouzuki, Kawasaki (Japan); Hironori Yoshioka, Yokohama (Japan); Ichiro Omura, Yokohama (Japan); and Wataru Saito, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Sep. 09, 2004, as Appl. No. 10/936,601. | ||
| Claims priority of application No. 2004-217640 (JP), filed on Jul. 26, 2004. | ||
| Prior Publication US 2006/0017096 A1, Jan. 26, 2006 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—409 [257/488; 257/620; 257/E29.007; 257/E29.017] | 17 Claims |
| 1. A semiconductor device, comprising:
a device active region defined for forming a semiconductor element in a semiconductor layer formed on a semiconductor substrate;
a terminal section formed in the periphery of said semiconductor layer on the semiconductor substrate to surround said device
active region, said terminal section including a trench formed in said semiconductor layer, having first and second opposing
sides, said first side located adjacent to said device active region, and a filler filled in said trench, and said terminal
section being adjacent to a dicing region; and
a field plate extended to above said trench from an electrode of said semiconductor element formed in said device active region,
wherein a tip of said field plate reaches said second side of said trench and does not come into contact with a region outside
of said active region.
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