a semiconductor substrate;

an element region having a semiconductor element, which includes an impurity layer and a trench, wherein the impurity layer is disposed in the trench, wherein the impurity layer includes an epitaxial impurity layer, and wherein the trench is disposed on a main surface of the semiconductor substrate; and

a field region disposed around the element region, wherein

the trench is an aggregation of a plurality of stripe line trenches so that the element region has a polygonal shape,

the field region includes a dummy trench disposed on a periphery of the element region,

the dummy trench is disposed along with at least one side of the polygonal shape on the periphery of the element region,

the dummy trench has a width substantially equal to a width of the trench in the element region,

the dummy trench has a longitudinal direction substantially equal to a longitudinal direction of the trench in the element region,

the field region further includes an impurity layer disposed in the dummy trench

the impurity layer of the field region includes an epitaxial impurity layer,

the semiconductor element in the element region includes:

a drift layer having a first conductive type and disposed in the trench of the element region;

a base layer having a second conductive type and disposed on the drift layer;

a source layer having the first conductive type and disposed on the base layer;

a MOS gate trench disposed on the main surface of the semiconductor substrate and penetrating the source layer and the base layer so that the MOS gate trench reaches the drift layer;

a gate insulation film disposed on an inner wall of the MOS gate trench;

a gate electrode disposed in the MOS gate trench through the gate insulation film;

a source electrode electrically connecting to the source layer and the base layer and

a drain electrode electrically connecting to the semiconductor substrate;

the drift layer, the base layer and the source layer are provided by the impurity layer,

both of the drift layer and the base layer are provided by the epitaxial impurity layer,

the impurity layer in the dummy trench only includes the drift layer, the base layer and the source layer without including the MOS gate trench, and

the source electrode is not connected to the source layer in the dummy trench so that the drift layer, the base layer and the source layer in the dummy trench are respectively isolated from the drift layer, the base layer and the source layer in the trench.