| US 7,564,076 B2 | ||
| Semiconductor device and manufacturing method therefor | ||
| Yoshihiko Hanamaki, Tokyo (Japan); Kenichi Ono, Tokyo (Japan); Masayoshi Takemi, Tokyo (Japan); and Makoto Takada, Osaka (Japan) | ||
| Assigned to MItsubishi Electric Corporation, Tokyo (Japan) | ||
| Filed on May 06, 2008, as Appl. No. 12/115,565. | ||
| Application 12/115565 is a division of application No. 11/549983, filed on Oct. 17, 2006, granted, now 7,394,114. | ||
| Claims priority of application No. 2006-148779 (JP), filed on May 29, 2006. | ||
| Prior Publication US 2008/0265275 A1, Oct. 30, 2008 | ||
| Int. Cl. H01L 33/00 (2006.01) | ||
| U.S. Cl. 257—200 [257/183; 257/201; 257/615; 257/E33.049] | 6 Claims |
| 1. A semiconductor device comprising:
a semiconductor substrate;
a first compound semiconductor layer disposed on and lattice-matched to said semiconductor substrate, said first compound
semiconductor layer containing a first Group V element and Group III elements including In;
a second compound semiconductor layer supported by said first compound semiconductor layer and containing a second Group V
element, excluding the first Group V element, and Group III elements excluding In; and
a third compound semiconductor layer disposed between said first and second compound semiconductor layers, said third compound
semiconductor layer forming a heterojunction with each of said first and second compound semiconductor layers, having the
same composition ratios of Group III elements as said second compound semiconductor layer, and having an equal or lower composition
ratio of the first Group V element than the composition ratio of the second Group V element.
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