| US 7,563,700 B2 | ||
| Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration | ||
| Anadi Srivastava, Austin, Tex. (US); Mark D. Hall, Austin, Tex. (US); Raghaw S. Rai, Austin, Tex. (US); and Jesse Yanez, New Braunfels, Tex. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Feb. 22, 2006, as Appl. No. 11/360,897. | ||
| Prior Publication US 2007/0197009 A1, Aug. 23, 2007 | ||
| Int. Cl. H01L 21/3205 (2006.01); H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—592 [257/E21.439] | 21 Claims |
| 1. A method for making a silicided gate structure, comprising:
providing a semiconductor substrate having a gate disposed thereon and having a spacer disposed adjacent to the gate;
subjecting the spacer to a first etch which exposes a first lateral portion of the gate;
creating an implant region adjacent to the spacer after the first etch;
subjecting the spacer to a second etch which exposes a second lateral portion of the gate; and
forming a layer of silicide over the first and second lateral portions of the gate.
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