| US 7,563,681 B2 | ||
| Double-gated non-volatile memory and methods for forming thereof | ||
| Craig T. Swift, Austin, Tex. (US); Thuy B. Dao, Austin, Tex. (US); and Michael A. Sadd, Austin, Tex. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Jan. 27, 2006, as Appl. No. 11/341,973. | ||
| Prior Publication US 2007/0178649 A1, Aug. 02, 2007 | ||
| Int. Cl. H01L 21/8234 (2006.01) | ||
| U.S. Cl. 438—283 [438/157; 438/176; 438/455; 257/E21.122; 257/E21.623] | 16 Claims |
| 1. A method of making a semiconductor device, the method comprising:
providing a first wafer comprising a first semiconductor layer and a first insulating layer on the first semiconductor layer;
providing a second wafer comprising a second insulating layer, a layer of gate material on the second insulating layer, a
first storage layer on the layer of gate material, and a semiconductor structure on the first storage layer;
bonding the first insulating layer to the second insulating layer;
cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding;
forming a second storage layer over the layer of the semiconductor structure; and
forming a top gate over the second storage layer, wherein the first and second storage layers comprise nanocrystals.
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