(a) preparing a semiconductor substrate having a first region where a memory device is formed and a second region where a logic device is formed;

(b) forming a first insulating layer on said semiconductor substrate;

(c) forming first through third contact plugs in said first insulating layer, said first and second contact plugs being electrically connected to said semiconductor substrate in said first region and having their upper surfaces exposed from said first insulating layer, said third contact plug being electrically connected to said semiconductor substrate in said second region and having its upper surface exposed from said first insulating layer;

(d) forming a second insulating layer on said first insulating layer and on said first through third contact plugs;

(e) forming a first opening in said second insulating layer to expose said first contact plug;

(f) forming a capacitor, which is in contact with said first contact plug, in said first opening;

(g) forming a third insulating layer on said second insulating layer to cover said capacitor;

(h) forming fourth and fifth contact plugs in said second and third insulating layers, said fourth contact plug being electrically connected to said second contact plug and having its upper surface exposed from said third insulating layer, said fifth contact plug being electrically connected to said third contact plug and having its upper surface exposed from said third insulating layer;

(i) forming a fourth insulating layer on said third insulating layer and on said fourth and fifth contact plugs;

(j) forming second and third openings in said fourth insulating layer to expose said fourth and fifth contact plugs, respectively; and

(k) forming a first copper interconnection which fills in said second opening and is electrically connected to said fourth contact plug, and a second copper interconnection which fills in said third opening and is electrically connected to said fifth contact plug.