| US 7,562,447 B2 | ||
| Method of manufacturing printed circuit board for fine circuit formation | ||
| Choon Keun Lee, Gyunggi-do (Korea, Republic of); Seung Hyun Ra, Gyunggi-do (Korea, Republic of); Sang Moon Lee, Seoul (Korea, Republic of); Jung Woo Lee, Gyunggi-do (Korea, Republic of); Jeong Bok Kwak, Gyunggi-do (Korea, Republic of); Jae Choon Cho, Gyunggi-do (Korea, Republic of); and Chi Seong Kim, Gyunggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electro-Mechanics Co., Ltd., Suwon (Korea, Republic of) | ||
| Filed on Mar. 27, 2007, as Appl. No. 11/727,587. | ||
| Claims priority of application No. 10-2006-0041518 (KR), filed on May 09, 2006. | ||
| Prior Publication US 2007/0264755 A1, Nov. 15, 2007 | ||
| Int. Cl. H01K 3/10 (2006.01) | ||
| U.S. Cl. 29—852 [29/846; 29/847] | 7 Claims |
| 1. A method of manufacturing a printed circuit board for fine circuit formation, comprising:
providing a printing circuit board, including a dielectric layer having a negative pattern for circuit formation containing
a via hole and a line, formed on at least one surface thereof;
forming a metal layer on the dielectric layer such that the metal layer is formed excessively thick on the dielectric layer
when loaded into the negative pattern of the dielectric layer;
removing a part of the metal layer formed on the dielectric layer through mechanical polishing until the metal layer formed
on the dielectric layer has a thickness of 0.1˜20 μm; and
removing the remaining metal layer formed on the dielectric layer through chemical etching, thus forming a circuit.
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