| US 7,562,327 B2 | ||
| Mask layout design improvement in gate width direction | ||
| Shinsaku Sekido, Osaka (Japan); Kyoji Yamashita, Kyoto (Japan); Katsuhiro Ootani, Nara (Japan); Yasuyuki Sahara, Kyoto (Japan); and Daisaku Ikoma, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Nov. 02, 2006, as Appl. No. 11/591,452. | ||
| Claims priority of application No. 2005-361370 (JP), filed on Dec. 15, 2005. | ||
| Prior Publication US 2007/0141766 A1, Jun. 21, 2007 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—10 [716/8; 716/9; 716/11; 438/129; 438/154; 438/199; 438/207; 438/223; 438/313; 257/206] | 12 Claims |
| 1. A semiconductor circuit device comprising a cell array formation region made of cells which are arranged in an array, each
cell having a first conductivity type MIS transistor and a second conductivity type MIS transistor, wherein
in the cell array formation region, a plurality of first conductivity type first wells and a plurality of second conductivity
type second wells are alternately arranged in a gate width direction,
a distance between an outer end portion of each outermost well of the first wells and the second wells in the gate width direction
in the cell array formation region, and an active region formed in the outermost well, is set to be larger than or equal to
a predetermined value,
an outermost well contact region is provided between the active region and the outer end portion of the outermost well, and
a distance from a boundary line between the outermost well and another well adjacent thereto, to the outer end portion of
the outermost well, is one time or more and two times or less larger than a distance from the boundary line to a center line
of the outermost well contact region.
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