| US 7,562,198 B2 | ||
| Semiconductor device and semiconductor signal processing apparatus | ||
| Hideyuki Noda, Hyogo (Japan); Kazunori Saitoh, Hyogo (Japan); Kazutami Ariomoto, Hyogo (Japan); and Katsumi Dosaka, Hyogo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Jun. 09, 2005, as Appl. No. 11/148,369. | ||
| Claims priority of application No. 2004-171658 (JP), filed on Jun. 09, 2004; application No. 2004-175193 (JP), filed on Jun. 14, 2004; application No. 2004-282449 (JP), filed on Sep. 28, 2004; and application No. 2005-143109 (JP), filed on May 16, 2005. | ||
| Prior Publication US 2005/0285862 A1, Dec. 29, 2005 | ||
| Int. Cl. G06F 21/22 (2006.01) | ||
| U.S. Cl. 711—154 | 22 Claims |
| 1. A semiconductor device, comprising:
a first processing unit;
an internal bus; and,
a plurality of operation units each comprising an operational block and an operational control unit,
wherein said first processing unit issues an instruction to the operation units via said internal bus,
wherein each operational block includes a memory array used for storing data and divided into plural entries, and a plurality
of first processing elements each of which is arranged corresponding to a respective entry of said memory array and is for
performing an arithmetic and logical operation,
wherein each of said plural first processing elements performs an operation instructed by said operational control unit using
data provided from first selected memory cells in corresponding entries in parallel and store result of said operation into
second selected memory cells in said corresponding entries in parallel, and
wherein said memory array has a first word line selected for activating the first selected memory cells of all the entries,
and has a second word line selected for activating said second selected memory cells of all the entries.
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