| US 7,562,111 B2 | ||
| Multi-processor architecture with high capacity I/O | ||
| Jack C. Wybenga, Plano, Tex. (US); Patricia K. Sturm, Marion, Iowa (US); and Mark Lang, Plano, Tex. (US) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si (Korea, Republic of) | ||
| Filed on Mar. 28, 2005, as Appl. No. 11/91,731. | ||
| Claims priority of provisional application 60/575589, filed on May 27, 2004. | ||
| Claims priority of provisional application 60/575590, filed on May 27, 2004. | ||
| Prior Publication US 2005/0267930 A1, Dec. 01, 2005 | ||
| Int. Cl. G06F 15/16 (2006.01) | ||
| U.S. Cl. 709—201 [709/227] | 20 Claims |
| 1. A data processing apparatus, comprising:
a main data processor capable running an application;
a plurality of subordinate data processors, each said subordinate data processor including an instruction execution unit which
executes program instructions in parallel and independently of said main data processor, where said program instructions are
received from said main data processor and perform data communication associated with execution of the application;
a plurality of communication paths which respectively couple said subordinate data processors to said main data processor;
and
each of said subordinate data processors responsive to execution of program instructions in its associated execution unit
for implementing a data communication channel that performs data communication with an external site that is physically separate
from said data processing apparatus, wherein said data communication with said external site is performed via an input/out
channel that is physically separate from said plurality of communication paths.
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