| US 7,560,964 B2 | ||
| Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility | ||
| David E. Lackey, Jericho, Vt. (US); Steven F. Oakland, Colchester, Vt. (US); and Peter Verwegen, Rottenburg (Germany) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Mar. 18, 2005, as Appl. No. 11/82,990. | ||
| Prior Publication US 2006/0208783 A1, Sep. 21, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03K 3/289 (2006.01) | ||
| U.S. Cl. 327—202 [327/203; 714/726] | 19 Claims |
| 1. An edge triggered system having a data and scan input, said system comprising:
a latch device having a clock input; and
an AND gate, coupled to said latch device, structured and arranged to receive a first clock signal and an inverted clock signal
to generate a clock to said clock input,
wherein the latch device and the AND gate are configured to provide mux-scan and LSSD testing capabilities,
wherein said latch device comprises at least a first and second latch, in which each latch has at least one clock input,
said second latch receiving data from the first latch,
said AND gate has an output that is coupled to said first latch, and a second clock signal is coupled to said clock input
of said second latch, and
said second clock signal is inverted to be the inverted clock signal to said AND gate.
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