| US 7,560,953 B1 | ||
| Power management systems and methods for programmable logic devices | ||
| Satwant Singh, Fremont, Calif. (US); Fabiano Fontana, San Jose, Calif. (US); and David Chang, Sunnyvale, Calif. (US) | ||
| Assigned to Lattice Semiconductor Corporation, Hillsboro, Oreg. (US) | ||
| Filed on Apr. 23, 2008, as Appl. No. 12/107,883. | ||
| Int. Cl. H03K 19/173 (2006.01) | ||
| U.S. Cl. 326—38 [326/82] | 20 Claims |
| 1. A programmable logic device comprising:
a plurality of logic blocks;
a plurality of input terminals;
a routing resource adapted to couple the logic blocks to the input terminals;
an input buffer disposed between a first input terminal and the routing resource, the input buffer having a buffer input terminal
and a buffer output terminal; and
a multiplexer disposed between the first input terminal and the input buffer, wherein the multiplexer is adapted to couple,
under control of a multiplexer control signal, the first input terminal to the buffer input terminal or to couple the buffer
output terminal to the buffer input terminal.
|