| US 7,560,772 B2 | ||
| Semiconductor integrated circuit device and manufacturing method thereof | ||
| Satoshi Sakai, Yokohama (Japan); Atsushi Hiraiwa, Higashimurayama (Japan); and Satoshi Yamamoto, Takarazuka (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Dec. 23, 2007, as Appl. No. 11/963,846. | ||
| Application 11/963846 is a continuation of application No. 10/496825, granted, now 7,335,561, previously published as PCT/JP01/10492, filed on Nov. 20, 2001. | ||
| Prior Publication US 2008/0105923 A1, May 08, 2008 | ||
| Int. Cl. H01L 29/76 (2006.01); H01L 21/8234 (2006.01); H01L 21/336 (2006.01) | ||
| U.S. Cl. 257—336 [438/275; 438/287] | 20 Claims |
| 1. A semiconductor integrated circuit device comprising:
a first MISFET formed in a first region of a semiconductor substrate; and
a second MISFET formed in a second region of the semiconductor substrate,
wherein the first MISFET includes:
a first insulation film formed over the first region;
a first portion of a third insulation film formed over the first insulation film;
a first gate electrode of the first MISFET formed over the first portion of the third insulation film;
wherein the second MISFET includes:
a second insulation film formed over the second region;
a second portion of the third insulation film formed over the second insulation film;
a second gate electrode of the second MISFET formed over the second portion of the third insulation film;
wherein the first and second insulation films include silicon, oxygen and nitrogen;
wherein the third insulation film has a greater dielectric constant than each of the first and second insulation films,
wherein a thickness of the first insulation film is larger than a thickness of the second insulation film; and
wherein a thickness of the third insulation film is greater than the thicknesses of the first insulation film and the second
insulation film.
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