| US 7,560,388 B2 | ||
| Self-aligned pitch reduction | ||
| Jisoo Kim, Pleasanton, Calif. (US); Sangheon Lee, Sunnyvale, Calif. (US); Daehan Choi, Sunnyvale, Calif. (US); and S. M. Reza Sadjadi, Saratoga, Calif. (US) | ||
| Assigned to Lam Research Corporation, Fremont, Calif. (US) | ||
| Filed on Nov. 30, 2005, as Appl. No. 11/291,303. | ||
| Prior Publication US 2007/0123053 A1, May 31, 2007 | ||
| Int. Cl. H01L 21/311 (2006.01) | ||
| U.S. Cl. 438—702 [438/241; 438/275; 438/587; 438/737; 257/E21.683] | 17 Claims |
| 1. A method providing features in a dielectric layer, comprising:
forming a sacrificial layer over the dielectric layer;
forming a patterned mask over the sacrificial layer;
etching a set of sacrificial layer features into the sacrificial layer;
shrinking the sacrificial layer features by forming a shrink deposition;
etching a first set of dielectric layer features into the dielectric layer through the sacrificial layer;
filling the features of the first set of dielectric layer features and the set of sacrificial layer features with a filler
material;
removing the sacrificial layer, so that parts of the filler material remain exposed above a surface of the dielectric layer,
wherein spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by
the sacrificial layer, wherein the spaces have widths;
shrinking the widths of the spaces between the parts of the filler material with a shrink sidewall deposition;
etching a second set of dielectric layer features into the dielectric layer through the shrink sidewall deposition; and
removing the filler material and shrink sidewall deposition.
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