forming a polysilicon layer for floating gates, and then forming an etching trench for device isolating region formation by selectively removing the polysilicon layer for floating gates;

forming a device isolating region by depositing an insulator film across the entire surface of the device for filling in the etching trench, and then planarizing until exposing the polysilicon layer for floating gates;

successively depositing an inter-gate insulating film, a control gate, and a mask insulator film across the entire planarized surface;

successively removing select gate transistors in an area other than a memory cell transistor area, the mask insulator in a peripheral transistor area, the control gate, and the inter-gate insulator film, and then etching the filling material of the device isolating region such that the surface of the device isolating region can be at a lower position than the bottom of the inter-gate insulator film;

depositing a conductive material for sidewall gates across the entire surface of the device, and then leaving only sidewall gates by selective etching; and

forming isolated memory cell transistor areas and select gate transistor areas.