| US 7,560,318 B2 | ||
| Process for forming an electronic device including semiconductor layers having different stresses | ||
| Mariam G. Sadaka, Austin, Tex. (US); Venkat R. Kolagunta, Austin, Tex. (US); William J. Taylor, Austin, Tex. (US); and Victor H. Vartanian, Austin, Tex. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Mar. 13, 2006, as Appl. No. 11/374,372. | ||
| Prior Publication US 2007/0210381 A1, Sep. 13, 2007 | ||
| Int. Cl. H01L 21/84 (2006.01) | ||
| U.S. Cl. 438—151 [438/285; 257/E21.561] | 20 Claims |
| 1. A process of forming an electronic device comprising:
providing a workpiece, wherein:
the workpiece includes a first semiconductor layer, an insulating layer, and a base layer;
the insulating layer lies between the first semiconductor layer and the base layer, and
the first semiconductor layer has a first stress, the first stress having a first magnitude and a first type;
forming a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a second
stress, the second stress having a second magnitude and a second type;
annealing the workpiece such that the second semiconductor layer has a third stress, the third stress having a third magnitude
and a third type, wherein the third magnitude is different than the second magnitude; and
removing at least a portion of the second semiconductor layer to expose a portion of the first semiconductor layer, wherein
after removing the at least a portion of the second semiconductor layer, the first semiconductor layer has a fourth stress,
the fourth stress having a fourth magnitude and a fourth type, and the fourth type is opposite the second type.
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