| US 7,560,293 B2 | ||
| Evaluation method using a TEG, a method of manufacturing a semiconductor device having the TEG, an element substrate and a panel having the TEG, a program for controlling dosage and a computer-readable recording medium recording the program | ||
| Etsuko Asano, Kanagawa (Japan); Osamu Nakamura, Kanagawa (Japan); and Masayuki Sakakura, Kanagawa (Japan) | ||
| Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-Ken (Japan) | ||
| Filed on Jul. 19, 2007, as Appl. No. 11/826,861. | ||
| Application 11/826861 is a division of application No. 10/735627, filed on Dec. 16, 2003, granted, now 7,256,079. | ||
| Claims priority of application No. 2002-364411 (JP), filed on Dec. 16, 2002. | ||
| Prior Publication US 2008/0026490 A1, Jan. 31, 2008 | ||
| Int. Cl. G01R 31/26 (2006.01); H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—18 [438/159] | 18 Claims |
| 1. A method of manufacturing a semiconductor device comprising:
forming a TFT including at least a semiconductor film having an impurity region and a gate electrode over a substrate, the
gate electrode being formed over the semiconductor film by using a mask;
forming a TEG including at least a semiconductor film having an impurity region over the substrate;
calculating misalignment of a mask of the TEG from an electric characteristics measurement of the TEG after an activation
step of the TFT; and
calculating shrinkage or expansion of the substrate by the calculated misalignment of the mask of the TEG.
|