	US 7,559,044 B2
	Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit
Atsuhiko Ikeuchi, Kawasaki (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Dec. 28, 2006, as Appl. No. 11/646,321.
Claims priority of application No. 2005-378920 (JP), filed on Dec. 28, 2005.
Prior Publication US 2007/0168895 A1, Jul. 19, 2007
Int. Cl. G06F 17/50 (2006.01)

U.S. Cl. 716—5 [716/2; 716/11; 716/12]

18 Claims

1. An automatic design method of a semiconductor integrated circuit comprising:

increasing an interval between a plurality of wiring patterns provided on a chip region to relieve a density of the wiring patterns based on first reference information including a criterion about a restriction of wiring length and second reference information including a criterion for a reduction of defect;

verifying a circuit characteristic for the result of the relief using a computer processor;

first thickening the wiring pattern by using a first design rule having a first correction value for thickening the wiring pattern; and

second thickening the wiring pattern having been thickened in said first thickening by using a second design rule having a second correction value higher than the first correction value.