| US 7,558,992 B2 | ||
| Reducing the soft error vulnerability of stored data | ||
| Oguz Ergin, Ankara (Turkey); Osman Unsal, Barcelona (Spain); Xavier Vera, Barcelona (Spain); and Antonio González, Barcelona (Spain) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Appl. No. 10/563,169 PCT Filed Oct. 10, 2005, PCT No. PCT/ES2005/070144 § 371(c)(1), (2), (4) Date Dec. 29, 2005, PCT Pub. No. WO2007/042581, PCT Pub. Date Apr. 19, 2007. |
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| Prior Publication US 2007/0094560 A1, Apr. 26, 2007 | ||
| Int. Cl. G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—701 [714/2; 714/3; 714/6; 714/42; 714/54; 714/718; 714/719; 714/746; 714/764; 714/799; 714/818; 714/819; 365/185.09; 365/201] | 21 Claims |
| 1. An apparatus comprising:
first storage logic to store a first portion of a dataword;
second storage logic to store a second portion of the dataword;
determination logic to determine a condition of the dataword;
third storage logic to store a result generated by the determination logic; and
selection logic to select, based on the contents of the third storage logic, one of the contents of the second storage logic
and a replacement value that depends on the contents of a predetermined bit of the first storage logic.
|